Semiconductor Devices and Technologies for Future Ultra Low Power Electronics

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D. Nirmal (Department of Electronics and Communication Engineering, Karunya University, Coimbatore, INDIA.) J. Ajayan (Department of Electronics and Communication Engineering, Karunya University, Coimbatore, INDIA.)

Semiconductor Devices and Technologies for Future Ultra Low Power Electronics

D. Nirmal (Department of Electronics and Communication Engineering, Karunya University, Coimbatore, INDIA.), J. Ajayan (Department of Electronics and Communication Engineering, Karunya University, Coimbatore, INDIA.), Patrick J. Fay (University of Notre Dame)

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English

CRC Press
04 October 2024

Circuits & components; Semi-conductors & super-conductors

This book covers the fundamentals and significance of 2-D materials and related semiconductor transistor technologies for the next-generation ultra low power applications. It provides comprehensive coverage on advanced low power transistors such as NCFETs, FinFETs, TFETs, and flexible transistors for future ultra low power applications owing to their better subthreshold swing and scalability. In addition, the text examines the use of field-effect transistors for biosensing applications and covers design considerations and compact modeling of advanced low power transistors such as NCFETs, FinFETs, and TFETs. TCAD simulation examples are also provided.

FEATURES

Discusses the latest updates in the field of ultra low power semiconductor transistors

Provides both experimental and analytical solutions for TFETs and NCFETs

Presents synthesis and fabrication processes for FinFETs

Reviews details on 2-D materials and 2-D transistors

Explores the application of FETs for biosensing in the healthcare field

This book is aimed at researchers, professionals, and graduate students in electrical engineering, electronics and communication engineering, electron devices, nanoelectronics and nanotechnology, microelectronics, and solid-state circuits.

Edited by: D. Nirmal (Department of Electronics and Communication Engineering Karunya University Coimbatore INDIA.), J. Ajayan (Department of Electronics and Communication Engineering, Karunya University, Coimbatore, INDIA.), Patrick J. Fay (University of Notre Dame)
Imprint: CRC Press
Country of Publication: United Kingdom
Dimensions: Height: 234mm, Width: 156mm,
Weight: 453g
ISBN: 9781032061627
ISBN 10: 1032061626
Pages: 290
Publication Date: 04 October 2024
Audience: Professional and scholarly , Undergraduate
Format: Paperback
Publisher's Status: Forthcoming

1. An Introduction to Nanoscale CMOS Technology Transistor. 2. High Performance Tunnel Field Effect Transistor (TFET) for Future Low Power Applications. 3. Ultra Low Power III-V Tunnel Field Effect Transistors. 4. Performance Analysis of Carbon Nanotube and Graphene Tunnel Field Effect Transistors. 5. Characterization of Silicon FinFETs Under Nanoscale Dimension. 6. Germenium or SiGe FinFETs for Enhanced Performance in Low Power Applications. 7. Switching Performance Analysis of III-V FinFET. 8. Negative Capacitance Field Effect Transistors to Address the Fundamental Limitations in Technology Scaling. 9. Recent Trends in Compact Modeling of Negative Capacitance Field Effect Transistors. 10. Fundamentals of 2D Materials. 11. Two-Dimensional Transition Metal Dichalcogenide (TMD) Materials in Field Effect Transistor (FET) Devices for Low Power Applications.

D. Nirmal is presently working as an Associate Professor and Head in the Department of Electronics and Communication engineering. His research interests includes Nanoelectronics, 1D/2D Materials, Carbon nanotubes, GaN Technology, Device and Circuit Simulation – GSL, Sensors, Nanoscale device design and modelling. J. Ajayan is an Associate Professor in the Department of Electronics and Communication Engineering at SR University, Telangana, India. His areas of interest are microelectronics, semiconductor devices, nanotechnology, RF integrated circuits and photovoltaics. Patrick Fay is currently a Professor with the Department of Electrical Engineering, University of Notre Dame, Notre Dame, IN, USA. He established the High Speed Circuits and Devices Laboratory, Notre Dame, and oversaw the design, construction, and commissioning of the 9000-ft2 class 100 cleanroom housed in Stinson-Remick Hall at Notre Dame. He has served as the Director of this facility since 2003.